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Volumn , Issue , 2010, Pages

The back-end electronics of the time projection chambers in the T2K experiment

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS SYSTEM; FLEXIBLE SYSTEM; FRONT END ELECTRONICS; GLOBAL DATA; NEUTRINO EXPERIMENTS; POWERPC PROCESSORS; REAL TIME; REFERENCE CLOCK; SOFTWARE IMPLEMENTATION; TIME PROJECTION CHAMBERS;

EID: 79956052906     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTC.2010.5750357     Document Type: Conference Paper
Times cited : (2)

References (10)
  • 2
    • 34250851781 scopus 로고    scopus 로고
    • A TPC for the near detector at T2K
    • Proc. 3rd Symposium on Large TPCs for Low Energy Rare Event Detection, 012018, IOP Publishing
    • T. Lux, "A TPC for the near detector at T2K", in Proc. 3rd Symposium on Large TPCs for Low Energy Rare Event Detection, Journal of Physics, Conference Series 65 (2007) 012018, IOP Publishing.
    • (2007) Journal of Physics, Conference Series , vol.65
    • Lux, T.1
  • 3
    • 45849096130 scopus 로고    scopus 로고
    • AFTER, an ASIC for the Readout of the Large T2K Time Projection Chambers
    • June
    • P. Baron et al., "AFTER, an ASIC for the Readout of the Large T2K Time Projection Chambers", IEEE Trans. Nucl. Sci., Volume: 55 No 3, June 2008, pp. 1744-1752.
    • (2008) IEEE Trans. Nucl. Sci. , vol.55 , Issue.3 , pp. 1744-1752
    • Baron, P.1
  • 4
    • 77951175778 scopus 로고    scopus 로고
    • Architecture and implementation of the front-end electronics of the time projection chambers in the T2K experiment
    • April
    • P. Baron et al., "Architecture and implementation of the front-end electronics of the time projection chambers in the T2K experiment", IEEE Trans. Nucl. Sci., Volume: 57 N° 2, April 2010, pp. 406-411.
    • (2010) IEEE Trans. Nucl. Sci. , vol.57 , Issue.2 , pp. 406-411
    • Baron, P.1
  • 6
    • 79956014840 scopus 로고    scopus 로고
    • UG210 (v1.2) March 21, [Online]. Available
    • Xilinx ML405 Evaluation Platform User Guide, UG210 (v1.2) March 21, 2007. [Online]. Available: http://www.xilinx.com
    • (2007) Xilinx ML405 Evaluation Platform User Guide
  • 7
    • 19344370988 scopus 로고    scopus 로고
    • Embedded Development Kit, Xilinx user guide UG018 (v2.4) January 11, [Online]. Available
    • PowerPC 405 Processor Block Reference Guide, Embedded Development Kit, Xilinx user guide UG018 (v2.4) January 11, 2010. [Online]. Available: http://www.xilinx.com
    • (2010) PowerPC 405 Processor Block Reference Guide
  • 10
    • 70350158651 scopus 로고    scopus 로고
    • High-Speed, Fixed-Latency Serial Links with FPGAs for Synchronous Transfers
    • October
    • A. Aloisio, F. Cevenini, R. Giordano, V. Izzo, "High-Speed, Fixed-Latency Serial Links With FPGAs for Synchronous Transfers", IEEE Trans. Nucl. Sci., Volume: 56 N° 5, October 2009, pp. 2864-2873.
    • (2009) IEEE Trans. Nucl. Sci. , vol.56 , Issue.5 , pp. 2864-2873
    • Aloisio, A.1    Cevenini, F.2    Giordano, R.3    Izzo, V.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.