Effects of film morphology and gate dielectric surface preparation on the electrical characteristics of organic-vapor-phase-deposited pentacene thin-film transistors

Applied Physics Letters

Volumn 81, Issue 2, 2002, Pages 268-270

  Shtein, Max ^a   Mapel, Jonathan ^a   Benziger, Jay B ^a   Forrest, Stephen R ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE GRAIN SIZE; CHAMBER PRESSURE; CRYSTALLINE GRAIN SIZE; DIELECTRIC SURFACE; ELECTRICAL CHARACTERISTIC; FIELD-EFFECT; FILM DEPOSITION; FILM MORPHOLOGY; MOLECULAR STACKS; OCTADECYLTRICHLOROSILANE; ON/OFF RATIO; ORGANIC VAPOR PHASE DEPOSITION; PENTACENE FILM; PENTACENE THIN-FILM TRANSISTORS; PENTACENES; POLYCRYSTALLINE PENTACENE; ROOM TEMPERATURE; SATURATION REGIME; SUBSTRATE TEMPERATURE; X-RAY DIFFRACTION STUDIES;

DRAIN CURRENT; FILM GROWTH; FILM PREPARATION; GATE DIELECTRICS; GRAIN GROWTH; GRAIN SIZE AND SHAPE; HOLE MOBILITY; PLASMA DEPOSITION; SILICON COMPOUNDS; SURFACE TREATMENT; THIN FILM TRANSISTORS; VAPORS; X RAY DIFFRACTION;

SEMICONDUCTING ORGANIC COMPOUNDS;

EID: 79956051443     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.1491009     Document Type: Article

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