Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 336-337

  Le Coz, Julien ^a   Flatresse, Philippe ^a   Engels, Sylvain ^a   Valentian, Alexandre ^b   Belleville, Marc ^b   Raynaud, Christine ^a   Croain, Damien ^a   Urard, Pascal ^a  

^a STMICROELECTRONICS   (France)

^b CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

SILICON ON INSULATOR TECHNOLOGY;

BULK TECHNOLOGIES; CRITICAL PROBLEMS; LEAKAGE CURRENT REDUCTION; LOW DENSITY PARITY CHECK; MAXIMUM FREQUENCY; PARTIALLY DEPLETED SOI; PD SOI TECHNOLOGY; POWER SWITCHING;

LOW POWER ELECTRONICS;

EID: 79955720317     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746343     Document Type: Conference Paper

References (5)

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2. R. Pottier, et al. "ARM 1176 implementation in SOI 45nm technology and silicon measurement," SOICONF, 2010.
3. J. Le-coz, et al. "Power Switch Optimization and Sizing in 65nm PD-SOI Considering Supply Voltage Noise," ICICDT, 2010.
4. F. Assaderaghi, et al. "A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation," IEEE Electron Device Letters, 1994.
5. S. V. Kosonocky, et al. "Low-power circuits and technology for wireless digital systems" IBM Journal of Research and Development, 2003.