GPU-based DVB-S2 LDPC decoder with high throughput and fast error floor detection

Electronics Letters

Volumn 47, Issue 9, 2011, Pages 542-543

  Falcao, G ^a   Andrade, J ^a   Silva, V ^a   Sousa, L ^b  

^a UNIVERSITY OF COIMBRA   (Portugal)

^b INSTITUTO SUPERIOR TÉCNICO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

CODE-WORDS; DVB-S2 STANDARD; ERROR FLOOR; GRAPHICS PROCESSING UNIT; HIGH-THROUGHPUT; IRREGULAR LDPC CODES; LDPC DECODER; MANY-CORE; MULTITHREADED; NEW STRATEGY;

COMPUTER GRAPHICS EQUIPMENT; ERROR CORRECTION; ERROR DETECTION; FLOORS; MEMORY ARCHITECTURE; PROGRAM PROCESSORS; THROUGHPUT;

DECODING;

EID: 79955639564     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el.2011.0201     Document Type: Article

References (9)

1. EN 302 307 V1. 1.1, European Telecommunications Standards Institute (ETSI). Digital video broadcasting (DVB); second generation framing structure, channel coding and modulation systems for broadcasting, interactive services, news gathering and other broad-band satellite applications
2. Lin, S., and Costello, D.J.: ' Error control coding ', (Prentice Hall, 2004)
3. Kienle, F., Brack, T., and Wehn, N.: ' A synthesizable IP core for DVB-S2 LDPC code decoding ', Proc. Design, Automation and Test in Europe (DATE), Munich, Germany, March, 2005, 3, p. 100-105 (Pubitemid 44172214)
4. Dielissen, J., Hekstra, A., and Berg, V.: ' Low cost LDPC decoder for DVBS2 ', Proc. Design, Automation and Test in Europe (DATE), Munich, Germany, March, 2006, 2, p. 1-6
5. Falcao, G., Sousa, L., and Silva, V.: ' Massively LDPC decoding on multicore architectures ', IEEE Trans. Parallel Distrib. Syst., 2011, 22, (2), p. 309-322 10.1109/TPDS.2010.66 1045-9219
6. Wang, S., Cheng, S., and Wu, Q.: ' A parallel decoding algorithm of LDPC codes using CUDA ', Proc. 42nd Asilomar Conf. on Signals, Systems and Computers, Pacific Grove, CA, USA, October, 2008, p. 171-175
7. Falcao, G., Silva, V., Sousa, L., and Marinho, J.: ' High coded data rate and multicodeword WiMAX LDPC decoding on Cell/BE ', Electron. Lett., 2008, 44, (24), p. 1415-1416 10.1049/el:20081927 0013-5194
8. Kirk, D., and Hwu, W.-M.: ' Programming massively parallel processors: a hands-on approach ', (Morgan Kaufmann, Burlington, MA, 2010)
9. Cai, Y., Jeon, S., Mai, K., and Kumar, B.V.K.V.: ' Highly parallel FPGA emulation for LDPC error floor characterization in perpendicular magnetic recording channel ', IEEE Trans. Magn., 2009, 45, (10), p. 3761-3764 10.1109/TMAG.2009.2022318 0018-9464