A general hardware design model for multicontext FPGAs

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2438 LNCS, Issue , 2002, Pages 1037-1047

  Kaneko, Naoto ^a   Amano, Hideharu ^a  

^a KEIO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE ARCHITECTURES; SCHEDULING;

ALGORITHMIC APPLICATIONS; CONTEXT MANAGEMENT; DEMAND-DRIVEN; DESIGN MODELING; HARDWARE DESIGN; NETWORK INTERFACE CONTROLLERS; SCHEDULING MECHANISM;

INTEGRATED CIRCUIT DESIGN;

EID: 79955127487     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-46117-5_106     Document Type: Conference Paper

References (5)

1. X.-P. Ling and H. Amano, "WASMII: A Data Driven Computer on a Virtual Hardware," Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pp. 33-42, 1993.
2. E. Caspi et al, "Stream Computations Organized for Reconfigurable Execution (SCORE)," Proceedings of the International Workshop on Field-Programmable Logic and Applications, pp. 605-614, 2000.
3. S. Trimberger "Scheduling Designs into a Time-Multiplexed FPGA," Proceedings of the IEEE Workshop on FPGA's for Custom Computing Machines, pp. 153-160, 1998.
4. M. Yamashina et al, "Reconfigurable Computing: Its concept and practical embodiment using newly developed DRL LSI," Proceedings of ASP-DAC, pp. 329-332, 2000.
5. K. Watanabe et al, "Preliminary Evaluation of Martini: a Novel Network Interface Controller Chip for Cluster-based Parallel Processing," Proceedings of International Symposium on Applied Informatics, pp.390-396, 2002.