Reconfigurable computing: Its concept and a practical embodiment using newly developed dynamically reconfigurable logic (DRL) LSI

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2000, Pages 329-332

  Yamashina, Masakazu ^a   Motomura, Masato ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMICALLY RECONFIGURABLE LOGIC; HARDWARE CONFIGURATIONS; PROTOTYPE CHIP; RECONFIGURABLE COMPUTING; SYSTEM LSI;

COMPUTER AIDED DESIGN; HARDWARE;

RECONFIGURABLE ARCHITECTURES;

EID: 77950388683     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368434.368666     Document Type: Conference Paper

References (17)

1. J. Villasenor and W. H. Mangione-Smith, "Configurable Computing," In Scientific American, Vol. 276, No. 6, pp. 54-59, June 1997.
2. W. H. Mangione-Smith, et al., "Seeking Solutions in Configurable Computing," In IEEE Computer, Vol. 30, No. 12, pp. 38-43, December 1997.
3. S. Hauck, "The Roles of FPGAs in Reprogrammable Systems", In Proceedings of the IEEE, Vol. 86, No. 4, pp. 615-638, April 1998.
4. D. Buell, J. Arnold, and W. Kleinfelder, "Splash2: FPGAs in a Custom Computing Machine", IEEE Computer Society Press, 1996.
5. X. Ling and H. Amano, "WASMII: An MPLD with Data-Driven Control on a Virtual Hardware, "In Journal of Supercomputing, Vol. 9, No. 3, pp. 253-276, 1995.
6. W. B. Andrew, et al., "A Field Programmable System Chip which Combines FPGA and ASIC Circuitry," In Proceedings of the IEEE 99 CICC, pp. 183-186, 1999.
7. A. DeHon, J. Wawrzynek. "Reconfigurable Computing: What, Why, and Design Automation Requirements?" In Proceedings of the 1999 Design Automation Conference, pages 610-615, June 1999.
8. A. DeHon, "Trends Toward Spatial Computing Architectures," In ISSCC Digest of Technical Papers, 21.2, Feb. 1999.
9. M. J. Alexander and M O'toole, "Implications of Reconfigurable VLSI in a Globally Networked World: Delivering Hardware Over the Net," Washington State Univ. Technical Report, EECS-97-003, Aug. 1997.
10. W. Lee, et al., "Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine," In Proceedings of the ASPLOS-8, October 1998.
11. A. Shibayama et al., "An Autonomous Reconfigurable Cell Array for Fault-Tolerant LSIs," In ISSCC Digest of Technical Papers, 14.4, Feb. 1997.
12. http://www.lightspeed.com/
13. M. Motomura, et al., "An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration," Proceedings of Symposium on VLSI Circuits, pp. 55-56, Jul. 1997.
14. S. Trimberger, et al., "A Time-Multiplexed FPGA," In Proceedings of Symposium on FCCM, pp. 22-28, Apr. 1997.
15. T. Fujii, et al., "A Dynamically Reconfigurable Logic Engine with a Multi-Context/Multi-Mode Unified-Cell Architecture," In ISSCC Digest of Technical Papers, 21.3, Feb. 1999.
16. T. Fujii, et al., "A 0.25-μm CMOS, 5.1-M-Transistor, Dynamically Reconfigurable Logic Engine (DRLE) LSI," In Proceedings of Cool Chips II, pp. 51-63, Apr.1999.
17. K.Wakabayashi, "Cyber: High Level Synthesis System from Software into ASIC," in High Level VLSI Synthesis, edited by R. Camposano and W. Wolf, Kluwer Academic Publisher, pp. 127-151, 1991.