A distributed Canny edge detector and its implementation on FPGA

2011 Digital Signal Processing and Signal Processing Education Meeting, DSP/SPE 2011 - Proceedings

Volumn , Issue , 2011, Pages 500-505

  Xu, Qian ^a   Chakrabarti, Chaitali ^a   Karam, Lina J ^a  

^a AZ 85281   (United States)

Author keywords

Canny Edge detector; Distributed Processing; FPGA; Non uniform quantization

Indexed keywords

CANNY ALGORITHM; CANNY EDGE DETECTION; CANNY EDGE DETECTORS; CLOCK RATE; DETECTION PERFORMANCE; DISTRIBUTED PROCESSING; EDGE DETECTION ALGORITHMS; FPGA; HARDWARE ARCHITECTURE; LOW-COMPLEXITY; NON-UNIFORM QUANTIZATION; NONUNIFORM; REDUCED MEMORY REQUIREMENTS; SIMULATION RESULT;

ALGORITHMS; DIGITAL SIGNAL PROCESSING; DISTRIBUTED PARAMETER NETWORKS; EDGE DETECTION; OBJECT RECOGNITION; SIGNAL DETECTION; SIGNAL PROCESSING;

DETECTORS;

EID: 79954547604     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSP-SPE.2011.5739265     Document Type: Conference Paper

References (6)

1. F. M. Alzahrani and T. Chen, "A real-time edge detector algorithm and VLSI architecture," Real-Time Imaging, vol. 3, no. 5, pp. 363 - 78, 1997. (Pubitemid 127666624)
2. L. Torres, M. Robert, E. Bourennane, and M. Paindavoine, "Implementation of a recursive real time edge detector using retiming techniques," VLSI, pp. 811-816, Aug. 1995.
3. D. V. Rao and M. Venkatesan, "An efficient reconfig-urable architecture and implementation of edge detection algorithm using Handle-C," ITCC, vol. 2, pp. 843 - 847, Apr. 2004.
4. S. Varadarajan, C. Chakrabarti, L. J. Karam, and J. M. Bauza, "A distributed psycho-visually motivated Canny edge detector," IEEE ICASSP, pp. 822-825, Mar. 2010.
5. J. Canny, "A computational approach to edge detection," IEEE Trans. PAMI, vol. 8, no. 6, pp. 679-698, Nov. 1986.
6. W. He and K. Yuan, "An improved Canny edge detector and its realization on FPGA," WCICA, pp. 6561-6564, Jun. 2008.