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Volumn , Issue , 2011, Pages

Normally-On SiC JFETs in power converters: Gate driver and safe operation

Author keywords

[No Author keywords available]

Indexed keywords

GATE DRIVERS; GATE DRIVING; PLUG-INS; SAFE OPERATION; SELF PROTECTION; VOLTAGE FED INVERTER;

EID: 79953734338     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (25)

References (15)
  • 1
    • 79953755962 scopus 로고    scopus 로고
    • Normally - On devices and circuits, SiC and high temperature : Using SiC JFETs in power converters
    • Berlin-Offenbach, CIPS
    • Dominique Bergogne, Bruno Allard, Dominique Planson, Dominique Tournier, Hervé Morel "Normally - On devices and circuits, SiC and high temperature : using SiC JFETs in power converters", VDE VERLAG GMBH, Berlin-Offenbach, CIPS 2008.
    • (2008) Vde Verlag Gmbh
    • Bergogne, D.1    Allard, B.2    Planson, D.3    Tournier, D.4    Morel, H.5
  • 2
    • 79953745536 scopus 로고    scopus 로고
    • A simple low cost gate drive method for practical use of SiCJFET in SMPS
    • Melkongan A., Hofsajer I., Round S.et Kolar J., "A simple low cost gate drive method for practical use of SiCJFET in SMPS", in "EPE Dresden", 2005.
    • (2005) EPE Dresden
    • Melkongan, A.1    Hofsajer, I.2    Round, S.3    Kolar, J.4
  • 3
    • 79953756562 scopus 로고    scopus 로고
    • Design of a gate drive circuit for use with SiC JFETs
    • Bjorn Allebrand et Hans Peter Nee, "Design of a Gate Drive Circuit For use with SiC JFETs", APEC, 2004.
    • (2004) APEC
    • Allebrand, B.1    Nee, H.P.2
  • 7
    • 2342476450 scopus 로고    scopus 로고
    • A novel SiC JFET gate drive circuit for sparse matrix converter applications
    • Marcelo L. Heldwein et Johann W.Kolar, "A novel SiC JFET gate drive circuit for sparse matrix converter applications", IEEE Trans. on Power Electronics, 2004.
    • (2004) IEEE Trans. on Power Electronics
    • Heldwein, M.L.1    Kolar, J.W.2
  • 13
    • 79953735319 scopus 로고    scopus 로고
    • Minimization of Drain-to-gate interaction in a SiC JFET inverter using an external gate-source capacitor
    • Nuremberg
    • O. Berry, Y. Hamieh, S. Raël, F. Meibody-Tabar, S. Vieillard, D. Bergogne, H. Morel, "Minimization of Drain-to-gate interaction in a SiC JFET inverter using an external gate-source capacitor", ICSCRM 2009, Nuremberg.
    • (2009) ICSCRM
    • Berry, O.1    Hamieh, Y.2    Raël, S.3    Meibody-Tabar, F.4    Vieillard, S.5    Bergogne, D.6    Morel, H.7


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.