Interfacing issues in real-time digital simulators

IEEE Transactions on Power Delivery

Volumn 26, Issue 2, 2011, Pages 1221-1230

  Ren, W ^b   Sloderbeck, M ^b   Steurer, M ^b   Dinavahi, V ^a   Noda, T ^b   Filizadeh, S ^b   Chevrefils, A R ^b   Matar, M ^b   Iravani, R ^b   Dufour, C ^b   Belanger, J ^b   Faruque, M O ^b   Strunz, K ^b   Martinez, J A ^b  

^a UNIVERSITY OF ALBERTA   (Canada)

^b NONE

Author keywords

Field programmable gate arrays (FPGAs); hardware in the loop simulation; interface algorithms; modeling; power system simulation; power electronic systems; real time systems

Indexed keywords

HARDWARE-IN-THE-LOOP SIMULATION; INTERFACE ALGORITHM; MODELING; POWER SYSTEM SIMULATION; POWER-ELECTRONIC SYSTEMS;

ALGORITHMS; ELECTRONICS ENGINEERING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; LOGIC GATES; SIMULATORS; SYNTHETIC APERTURES;

REAL TIME SYSTEMS;

EID: 79953193023     PISSN: 08858977     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPWRD.2010.2072792     Document Type: Article

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