A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2011, Pages 83-84

  Furuta, J ^a   Hamanaka, C ^b   Kobayashi, K ^b   Onodera, H ^a  

^a KYOTO UNIVERSITY   (Japan)

^b KYOTO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH-ENERGY NEUTRON; MULTIPLE CELL UPSET; RADIATION HARDNESS; SINGLE EVENT UPSETS; SOFT ERROR;

ALPHA PARTICLES; FLIP FLOP CIRCUITS; HIGH ENERGY PHYSICS;

COMPUTER AIDED DESIGN;

EID: 79952970042     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2011.5722306     Document Type: Conference Paper

References (4)

1. S. Mitra et. al. "Combinational Logic Soft Error Correction", International Test Conference, pp. 1-9, 2006.
2. N. Mikami et. al. "Role of the Deep Parasitic Bipolar Device in Mitigating the Single Event Transient Phenomenon", Reliability Physics Symposium, pp. 936-939, 2009.
3. S. Idgunji et. al. "Case Study of a Low Power MTCMOS Based ARM926 SoC : Design, Analysis and Test Challenges", International Test Conference, pp. 1-10, 2007.
4. J. Furuta et. al. "A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element", VLSI Circuit Symposium, pp. 123-124, 2010.