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Volumn , Issue , 2009, Pages 936-939
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Role of the deep parasitic bipolar device in mitigating the single event transient phenomenon
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Author keywords
Logic circuit; Parasitic bipolar transistor; SER; SET; SEU; Single event transient; Single Event Upset; Soft error rate
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Indexed keywords
PARASITIC BIPOLAR TRANSISTOR;
SER;
SET;
SEU;
SINGLE EVENT TRANSIENT;
SINGLE EVENT UPSET;
SOFT ERROR RATE;
BIPOLAR TRANSISTORS;
ELECTRIC NETWORK ANALYSIS;
MOS DEVICES;
SWITCHING CIRCUITS;
TRANSIENTS;
URANIUM POWDER METALLURGY;
LOGIC CIRCUITS;
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EID: 70449108050
PISSN: 15417026
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/IRPS.2009.5173384 Document Type: Conference Paper |
Times cited : (7)
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References (7)
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