Balanced truncation for time-delay systems via approximate gramians

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2011, Pages 55-60

  Wang, Xiang ^a   Wang, Qing ^a,b   Zhang, Zheng ^a,c   Chen, Quan ^a   Wong, Ngai ^a  

^a UNIVERSITY OF HONG KONG   (Hong Kong)

^b SUN YAT SEN UNIVERSITY   (China)

^c Department of Electrical Engineering and Computer Science   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BALANCED TRUNCATION; COMPUTATIONAL COSTS; DELAY ELEMENTS; FREQUENCY DOMAINS; GRAMIANS; LYAPUNOV; NEW MODEL; NUMERICAL EXAMPLE; OBSERVABILITY GRAMIANS; REDUCED ORDER MODELS; RLC NETWORKS; STATE TIME DELAY; TIME-DELAY SYSTEMS; TRANSMISSION LINE;

ALGORITHMS; CIRCUIT SIMULATION; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; CONTROLLABILITY; DELAY CIRCUITS; DELAY CONTROL SYSTEMS;

TIME DELAY;

EID: 79952925430     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2011.5722251     Document Type: Conference Paper

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