Passive order reduction for RLC circuits with delay elements

IEEE Transactions on Advanced Packaging

Volumn 30, Issue 4, 2007, Pages 830-840

  Tseng, Wenliang ^a   Chen, Changzhong ^b   Gad, Emad ^c   Nakhla, Michel ^b   Achar, Ramachandra ^b  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

^b CARLETON UNIVERSITY   (Canada)

^c UNIVERSITY OF OTTAWA   (Canada)

Author keywords

High speed interconnect; Macromodeling; Model order reduction delay system; Passivity

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; INTERCONNECTION NETWORKS; PASSIVE NETWORKS;

HIGH-SPEED INTERCONNECT; MACROMODELING; MODEL-ORDER REDUCTION DELAY SYSTEM; PASSIVITY;

DELAY CIRCUITS;

EID: 36349028694     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2007.906240     Document Type: Article

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