A phase synchronization and magnitude processor VLSI architecture for adaptive neural stimulation

2010 IEEE Biomedical Circuits and Systems Conference, BioCAS 2010

Volumn , Issue , 2010, Pages 5-8

  Abdelhalim, Karim ^a   Smolyakov, Vadim ^a   Genov, Roman ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL THROUGHPUT; CLOSED-LOOP; CMOS TECHNOLOGY; INPUT CHANNELS; INPUT SIGNAL; LOW POWER; NEURAL STIMULATIONS; PHASE SYNCHRONIZATION; PROCESSING CORE; REAL TIME; SAMPLING RATES; SHIFT-AND-ADD OPERATIONS; VLSI ARCHITECTURES; VLSI PROCESSOR ARCHITECTURE;

ARCHITECTURE; CMOS INTEGRATED CIRCUITS; ELECTROPHYSIOLOGY; VLSI CIRCUITS;

COMPUTER ARCHITECTURE;

EID: 79952381023     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BIOCAS.2010.5709557     Document Type: Conference Paper

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