Next generation eWLB (embedded wafer level BGA) packaging

2010 12th Electronics Packaging Technology Conference, EPTC 2010

Volumn , Issue , 2010, Pages 520-526

  Jin, Yonggang ^a   Baraton, Xavier ^a   Yoon, S W ^b   Lin, Yaojian ^b   Marimuthu, Pandi C ^b   Ganesh, V P ^c   Meyer, Thorsten ^c   Bahr, Andreas ^c  

^a STMICROELECTRONICS   (Singapore)

^b STATS CHIPPAC LTD   (Singapore)

^c INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BATCH PROCESS; BOARD-LEVEL RELIABILITY; DISCRETE COMPONENTS; DROP TEST; FAN-OUT; KEY TECHNOLOGIES; MATERIAL PROPERTY; MECHANICAL CHARACTERIZATIONS; ON-WAFER; OVERALL COSTS; PACKAGE RELIABILITY; PACKAGE SIZE; PROCESS FLOWS; TEMPERATURE CYCLES; THROUGH-SILICON-VIA; VERTICAL INTERCONNECTIONS; WAFER LEVEL; WAFER LEVEL PACKAGING;

BATCH DATA PROCESSING; INTERNET PROTOCOLS; PACKAGING; SILICON WAFERS; SUPPLY CHAINS; TECHNOLOGY; THREE DIMENSIONAL;

ELECTRONICS PACKAGING;

EID: 79951914193     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2010.5702695     Document Type: Conference Paper

References (9)

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