Estimation of maximum temperature in 3D-integrated package by thermal network method

2010 12th Electronics Packaging Technology Conference, EPTC 2010

Volumn , Issue , 2010, Pages 68-71

  Hatakeyama, Tomoyuki ^a   Ishizuka, Masaru ^a   Nakagawa, Shinji ^a  

^a TOYAMA PREFECTURAL UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CFD (COMPUTATIONAL FLUID DYNAMICS); COMPLEX STRUCTURE; COMPUTATIONAL TIME; INTER-CHIP; MAXIMUM TEMPERATURE; MULTI-LAYERED STRUCTURE; PARAMETRIC STUDY; TEMPERATURE MANAGEMENT; THERMAL DESIGNS; THERMAL NETWORK ANALYSIS; THERMAL NETWORK METHODS; UNDERFILL RESINS;

COMPUTATIONAL FLUID DYNAMICS; DESIGN; ELECTRIC NETWORK ANALYSIS; ELECTRONIC EQUIPMENT MANUFACTURE; PACKAGING; RESINS; THREE DIMENSIONAL;

CHIP SCALE PACKAGES;

EID: 79951883913     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2010.5702607     Document Type: Conference Paper

References (5)

1. Kada, M. "Development of Functionally Innovative 3D-Integrated Circuit (Dream Chip) Technology", Proc. of 3DIC 2009, San Francisco, CA, September 2009, pp. 1-6
2. Matsumoto, K., Ibaraki, S., Sakuma, K. and Yamada, F., "Thermal Resistance Measurement of Interconnections for a Three-Dimensional (3D) chip stack", Proc. of 3DIC 2009, San Francisco, CA, September 2009, pp. 11-7
3. Ishizuka, M., Nakagawa, S., Yoshida, T. and Nakayama, W., "Synthesis of CFD Analysis and Experiments in Developing a Thermal Network Model of a Siulated Heat Spreader Panel", Proc. of IMECE08, Boston, MA, November 2008, IMECE2008-66091
4. Hatakeyama, T., Ishizuka, M., Nakagawa, S. and Watanabe, K., "Development of Practical Thermal Design Techniqu of Printed Circuit Boards for Power Electronics", Proc. of ITherm2010, Las Vegas, NV, June 2010
5. th Edition, JSME (Tokyo, 2009)