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Volumn , Issue , 2010, Pages 347-350

SplitPro: A tool to overcome systemC scheduling inefficiencies

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK CYCLES; SIMULATION SPEED; SYSTEMC;

EID: 79951691999     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICM.2010.5696157     Document Type: Conference Paper
Times cited : (1)

References (5)
  • 5
    • 0029503205 scopus 로고
    • Use of embedded scheduling to compile VHDL for effective parallel simulation
    • Brighton, England, IEEE, Sep.
    • J Willis, Z. Li, and T. Lin, "Use of Embedded Scheduling to Compile VHDL for Effective Parallel Simulation," Proc. Conf on European Design Automation, Brighton, England, IEEE, Sep. 1995.
    • (1995) Proc. Conf on European Design Automation
    • Willis, J.1    Li, Z.2    Lin, T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.