A hardware architecture of Prewitt edge detection

IEEE Conference on Sustainable Utilization and Development in Engineering and Technology 2010, STUDENT 2010 - Conference Booklet

Volumn , Issue , 2010, Pages 99-101

  Seif, Aramesh ^a   Salut, Mohammad Mohammadpour ^a   Marsono, Muhammad Nadzir ^a  

^a UNIVERSITI TEKNOLOGI MALAYSIA   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCY; COMPUTATIONAL ERROR; FRAMES PER SECONDS; HARDWARE ARCHITECTURE; HARDWARE DESIGN; HIGH-SPEED IMAGE PROCESSING; IMAGE PROCESSING AND COMPUTER VISION; MATLAB- SOFTWARE; PREWITT EDGE DETECTION; PROPOSED ARCHITECTURES; SOFTWARE PARTS; VERILOG HARDWARE DESCRIPTION LANGUAGES;

COMPUTER APPLICATIONS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER OPERATING SYSTEMS; COMPUTER VISION; EDGE DETECTION; ERROR ANALYSIS; IMAGING SYSTEMS;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 79851493709     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/STUDENT.2010.5686999     Document Type: Conference Paper

References (5)

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5. T. A. Abbasi and M. U. Abassi, "A Novel Architecture for Prewitt Edge Detector," J. of Active and Passive Electronic Devices, Vol. 8, July 2009,pp. 203-211.