Multi-dimensional packet classification on FPGA: 100 Gbps and beyond

Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10

Volumn , Issue , 2010, Pages 241-248

  Qi, Yaxuan ^a   Fong, Jeffrey ^a   Jiang, Weirong ^c   Xu, Bo ^a   Li, Jun ^a,b   Prasanna, Viktor ^c  

^a Research Institute of Information Technology   (China)

^b TSINGHUA UNIVERSITY   (China)

^c University of Southern California ^*  (United States)

Author keywords

FPGA; Packet classification; Pipeline

Indexed keywords

CLOCK CYCLES; FPGA; FPGA DESIGN; FPGA-BASED ARCHITECTURES; INTRUSION PREVENTION; MEMORY REQUIREMENTS; MEMORY USAGE; MERGING ALGORITHMS; MULTI CORE; MULTI-DIMENSIONAL PACKETS; NETWORK APPLICATIONS; NETWORK BANDWIDTH; NEXT GENERATION NETWORK; ON-THE-FLY; PACKET CLASSIFICATION; PIPELINE ARCHITECTURE; RAPID GROWTH; THROUGHPUT PERFORMANCE; TRAFFIC MANAGEMENT SYSTEMS; TREE SEARCH ALGORITHM;

ALGORITHMS; ARTS COMPUTING; COMPUTER SYSTEM FIREWALLS; NETWORK ARCHITECTURE; PACKET NETWORKS; PIPELINES; TREES (MATHEMATICS);

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 79551513947     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2010.5681492     Document Type: Conference Paper

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