High-performance packet classification algorithm for many-core and multithreaded network processor

CASES 2006: International Conference on Compilers, Architecture and Synthesis for Embedded Systems

Volumn , Issue , 2006, Pages 334-344

  Liu, Duo ^a   Hua, Bei ^a   Hu, Xianghui ^a   Tang, Xinan ^b  

^a UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA   (China)

^b INTEL CORPORATION   (United States)

Author keywords

Architecture; Embedded system design; Multithreading; Network processor; Packet classification; Thread level parallelism

Indexed keywords

LATENCY HIDING; NETWORK PROCESSOR; RECURSIVE FLOW CLASSIFICATION (RFC) ALGORITHM;

ALGORITHMS; CLASSIFICATION (OF INFORMATION); EMBEDDED SYSTEMS; PROGRAM PROCESSORS; RECURSIVE FUNCTIONS;

PACKET NETWORKS;

EID: 34547225092     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1176760.1176801     Document Type: Conference Paper

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