A 4.9-GHz low power, low jitter, LC phase locked loop

Journal of Instrumentation

Volumn 5, Issue 12, 2010, Pages

  Liu, T ^a  

^a SOUTHERN METHODIST UNIVERSITY   (United States)

Author keywords

Analogue electronic circuits; Front end electronics for detector readout; VLSI circuits

Indexed keywords

EID: 78751485451     PISSN: 17480221     EISSN: 17480221     Source Type: Journal    
DOI: 10.1088/1748-0221/5/12/C12045     Document Type: Article

References (3)

1. A. Straessner, Development of new readout electronics for the ATLAS LAr calorimeter at the sLHC, presented at the Topical Workshop on Electronics in Particle Physics 2009 (TWEPP-09), September 21-25, Paris, France (2009).
2. D. Gong, A 16:1 serializer ASIC for data transmission at 5 Gbps, presented at the Topical Workshop on Electronics for Particle Physics 2010 (TWEEP-10), September 20-24, Aachen, Germany (2010).
3. T. Liu et al, The design of a high speed low power phase locked loop, presented at the Topical Workshop on Electronics in Particle Physics 2009 (TWEPP-09), September 21-25, Paris, France (2009).