Fault tolerant implementation of xilinx vertex FPGA for sensor systems through on-chip system evolution

Communications in Computer and Information Science

Volumn 120 CCIS, Issue PART 2, 2010, Pages 459-468

  Anandaraj, S P ^a   Kumar, R Naveen ^b   Ravi, S ^c   Sharma, S S V N ^b  

^a ST PETER S UNIVERSITY   (India)

^b KAKATIYA UNIVERSITY   (India)

^c DR M G R EDUCATIONAL AND RESEARCH INSTITUTE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; COMPUTER CIRCUITS; DIGITAL DEVICES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE;

DIGITAL LOGIC CIRCUIT; EFFECTIVE PARAMETERS; EVOLVABLE HARDWARE; FITNESS COMPUTATION; PHYSICAL DEVICES; POWERPC PROCESSORS; STRUCTURAL MODELS; TIME CONSUMPTION;

EVOLUTIONARY ALGORITHMS;

EID: 78651113267     PISSN: 18650929     EISSN: None     Source Type: Book Series    
DOI: 10.1007/978-3-642-17604-3_53     Document Type: Conference Paper

References (14)

1. Hollingsworth, G., Smith, S., Tyrrell, A.: Design of Highly Parallel Edge Detection Nodes using Evolutionary Techniques. In: Proceedings of the 7th Euro Micro Workshop on Parallel and Distributed Processing, pp. 35-42. IEEE, Los Alamitos (1999)
2. Layzell, P.: Reducing Hardware Evolution's Dependency on FPGAs. In: Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and Bio- Inspired Systems (Micron euro 1999), pp. 171-178. IEEE, Los Alamitos (1999)
3. Clark, G.R.: A Novel Function-Level EHW Architecture within Modern FPGAs. In: Proceedings of the Congress on Evolutionary Computation (CEC 1999). IEEE, Los Alamitos (1999);
4. Hollingworth, G., Smith, S., Tyrrell, A.: Safe Intrinsic Evolution of Virtex Devices. In: Proceedings of the Second NASA/DoD Workshop on Evolvable Hardware, pp. 195-202. IEEE, Los Alamitos (2000)
5. Thompson, A., Harvey, I., Husbands, P.: The natural way to evolve hardware. In: Proc. IEEE Int. Symp. Circuits Syst., pp. 37-40 (1996)
6. Hereford, J., Pruitt, C.: Robust sensor systems using evolvable hardware. In: Proc. NASA/DoD Conf. Evolvable Hardware, Seattle, WA, pp. 161-168 (June 2004)
7. Thompson, A., Harvey, I., Husbands, P.: The natural way to evolve hardware. In: Proc. IEEE Int. Symp. Circuits Syst., pp. 37-40 (1996)
8. Sun, X., Xu, J., Chan, B., Trouborst, P.: Novel Technique for Built-In Self-Test of FPGA Interconnects. In: Proc. Of IEEE International Test Conference, pp. 795-803 (2000)
9. Programmable Data Book, Xilinx Inc. (2003)
10. Renovell, M., Portal, J.M., Figuras, J., Zorian, Y.: Testing the Interconnect of RAM-Based FPGAs. In: IEEE Designand Test of Computers, pp. 45-50 (1998)
11. Feng, W., Chen, X., Meyer, F.J., Lombardi, F.: Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources. In: Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 368-376 (1999)
12. Sekanina, L.: Toward uniform approach to design of evolvable hardware based systems. In: Grünbacher, H., Hartenstein, R.W. (eds.) FPL 2000. LNCS, vol. 1896, pp. 814-817. Springer, Heidelberg (2000)
13. Torresen, J.: Possibilities and limitations of applying evolvable hardware to real-world application
14. Hartenstein, R.W., et al. (eds.): FPL 2000. LNCS, vol. 1896, pp. 230-239. Springer, Heidelberg (2000)