A scalable parallel hardware architecture for connected component labeling

Proceedings - International Conference on Image Processing, ICIP

Volumn , Issue , 2010, Pages 3753-3756

  Lin, Chung Yuan ^a   Li, Sz Yan ^a   Tsai, Tsung Han ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

Connected component; Labeling algorithm; Real time; Scalable architecture

Indexed keywords

CONNECTED COMPONENT; CONNECTED COMPONENT LABELING; FOREST STRUCTURE; HIGH THROUGHPUT; HIGH-DIMENSIONAL IMAGES; LABELING ALGORITHM; LABELING PROCEDURES; MEMORY REQUIREMENTS; NOVEL DESIGN; PARALLEL HARDWARE; PARALLEL-CONNECTED; PROCESS UNIT; PROPOSED ARCHITECTURES; RASTER SCANS; REAL-TIME; SCALABLE ARCHITECTURES; SEQUENTIALITY;

ALGORITHMS; IMAGING SYSTEMS;

IMAGE PROCESSING;

EID: 78651075320     PISSN: 15224880     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICIP.2010.5653457     Document Type: Conference Paper

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