Area- and throughput-optimized VLSI architecture of sphere decoding

Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010

Volumn , Issue , 2010, Pages 189-194

  Wenk, Markus ^a   Bruderer, Lukas ^a   Burg, Andreas ^a   Studer, Christoph ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY PRODUCT; IEEE 802.11N; MIMO COMMUNICATION SYSTEM; MULTIPLE-INPUT-MULTIPLE-OUTPUT; PERFORMANCE DATA; REGISTER TRANSFER LEVEL; SOFT OUTPUT; SPHERE DECODING; VLSI ARCHITECTURES; VLSI IMPLEMENTATION; WIDE-BAND; WIRELESS COMMUNICATION SYSTEM;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMMUNICATION SYSTEMS; DECODING; GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS; MIMO SYSTEMS; OPTIMIZATION; SPHERES; STANDARDS; WIRELESS TELECOMMUNICATION SYSTEMS;

PROGRAMMABLE LOGIC CONTROLLERS;

EID: 78650928041     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2010.5642593     Document Type: Conference Paper

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