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Volumn , Issue , 2006, Pages 397-400
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A pipelined VLSI architecture for a list sphere decoder
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Author keywords
[No Author keywords available]
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Indexed keywords
CLOCKS;
COMMUNICATION CHANNELS (INFORMATION THEORY);
DECODING;
ITERATIVE METHODS;
METRIC SYSTEM;
CLOCK FREQUENCY;
LIST SPHERE DECODER (LSD);
MIMO CHANNELS;
ONE NODE PER CYCLE POLICY;
VLSI CIRCUITS;
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EID: 34547291178
PISSN: 02714310
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (14)
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References (6)
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