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Proceedings - 15th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2010

Volumn , Issue , 2010, Pages 171-172

Hardware-based reliability tree (HRT) for fault tree analysis

(2) Rajabzadeh, Amir a Jahangiry, Mohammad S a

a RAZI UNIVERSITY (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATING TIME; COMPLEX SYSTEMS; CONTINUOUS TIME; CRITICAL SYSTEMS; CUT SETS; FAULT-TREES; LARGE SYSTEM; MARKOV CHAIN; MULTIPLIER CIRCUITS; RELIABILITY CALCULATION; SECURITY ALARM SYSTEM; SPEED-UPS; TWO PROCESSORS;

ALARM SYSTEMS; BAYESIAN NETWORKS; BINARY DECISION DIAGRAMS; BINARY TREES; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; CONTINUOUS TIME SYSTEMS; EQUIVALENT CIRCUITS; FAULT TREE ANALYSIS; HARDWARE; INFERENCE ENGINES; MARKOV PROCESSES; MULTIPROCESSING SYSTEMS; NETWORK ARCHITECTURE; RELIABILITY ANALYSIS; SECURITY OF DATA;

QUALITY ASSURANCE;

EID: 78650120484 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/CADS.2010.5623587 Document Type: Conference Paper

Times cited : (1)

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