Dual channel and strain for CMOS co-integration in FDSOI device architecture

2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010

Volumn , Issue , 2010, Pages 206-209

  Le Royer, C ^a   Case M ^a   Andrieu, F ^a   Weber, O ^a   Brevard, L ^a   Perreau, P ^a   Damlencourt, J F ^a   Baudot, S ^a   Tabone, C ^a   Allain, F ^a   Scheiblin, P ^a   Rauer, C ^a   Hutin, L ^a   Figuet, C ^a,b   Aulnette, C ^a,b   Daval, N ^a,b   Nguyen, B Y ^a,b   Bourdelle, K K ^a,b  

^a CEA LETI   (France)

^b PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COINTEGRATION; DEVICE ARCHITECTURES; DUAL CHANNEL; FULLY DEPLETED; GATE LENGTH; GATE STACKS; METAL GATE; SHORT CHANNELS;

SOLID STATE DEVICES;

INTEGRATION;

EID: 78649954028     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2010.5618388     Document Type: Conference Paper

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