FPGA architecture for real-time video noise estimation

Proceedings - International Conference on Image Processing, ICIP

Volumn , Issue , 2006, Pages 3257-3260

  Lapalme, François Xavier ^a   Amer, Aishy ^a   Wang, Chunyan ^a  

^a Dept of Electrical and Computer Engineering   (Canada)

Author keywords

Estimation; Field programmable gate arrays; Video signal processing; White noise

Indexed keywords

ADDITIONAL FLEXIBILITIES; ESTIMATION ERRORS; FPGA ARCHITECTURES; FPGA DEVICES; HARDWARE ARCHITECTURE; IMAGE STRUCTURES; NOISE ESTIMATION; NOISE ESTIMATION ALGORITHM; NOISE VARIANCE; PROCESSING SPEED; PROPOSED ARCHITECTURES; REAL TIME PERFORMANCE; REAL TIME VIDEOS; REALTIME PROCESSING; SPATIAL NOISE; TEXTURED IMAGES; VHDL IMPLEMENTATION; VIDEO NOISE ESTIMATION; VIDEO SEQUENCES; VIDEO SIGNAL;

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE PROCESSING; IMAGING SYSTEMS; LOGIC GATES; SIGNAL PROCESSING; VIDEO RECORDING; VIDEO SIGNAL PROCESSING; WHITE NOISE;

ESTIMATION;

EID: 78649840896     PISSN: 15224880     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICIP.2006.312918     Document Type: Conference Paper

References (7)

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