A 9μW 88dB DR fully-clocked switched-opamp ΔΣ modulator with novel power and area efficient resonator

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2010, Pages

  Xu, Jian ^a   Wu, Xiaobo ^a   Wang, Hanqing ^a   Liu, Bill ^b   Zhao, Menglian ^a  

^a ZHEJIANG UNIVERSITY   (China)

^b Analog Devices   (China)

Author keywords

[No Author keywords available]

Indexed keywords

1/F NOISE; A-COEFFICIENT; AREA EFFICIENT; AREA REDUCTION; CMOS PROCESSS; CONVENTIONAL DESIGN; EFFICIENT METHOD; FIGURE OF MERIT; LOW COSTS; LOW POWER; POWER SAVINGS; TOTAL POWER; VOLTAGE GAIN;

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; OPERATIONAL AMPLIFIERS; RESONATORS;

MODULATORS;

EID: 78649805196     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2010.5617458     Document Type: Conference Paper

References (7)

1. Jiang Yu and Franco Maloberti, "A Low-Power Multi-Bit ΔΣ Modulator in 90nm Digital CMOS without DEM", ISSCC Dig. Tech. Papers, pp.168-169, Feb. 2005.
2. Ahmed Gharbiya and David A. Johns, "A 12-bit 3.125 MHz Bandwidth 0-3 MASH Delta-Sigma Modulator", IEEE J. Solid-State Circuits, Volume 44, pp.2010 - 2018, July 2009.
3. Jens Sauerbrey, Thomas Tille, Doris Schmitt-Landsiedel and Roland Thewes, "A 0.7V MOSFET-only switched-opamp ΣΔ modulator", ISSCC Dig. Tech. Papers, pp.168-169, Feb. 2002.
4. Libin Yao, Michiel S. J. Steyaert and Willy Sansen, "A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90- nm CMOS", IEEE J. Solid-State Circuits, vol. 39, no. 11, pp.1809-1818, Nov. 2004.
5. J. Roh, S. Byun, Y. Choi, H. Roh, Y.-G. Kim and J.-K. Kee, "A 0.9-V 60-μW 1-Bit Fourth-Order Delta-Sigma Modulator with 83-dB Dynamic Range," IEEE J. Solid- State Circuits, vol. 43, no. 2, pp. 361-370, Feb. 2008.
6. Jian Xu, Hanqing Wang, and Xiaobo Wu, "A 20μW 95dB DR Single-Bit Delta-Sigma Modulator for Portable Measurement Applications", 2010 IAENG International Conference on Electrical Engineering, pp.1227-1232, Mar. 2010.
7. K. Nagaraj, "A Parasitic-Insensitive Area-Efficient Approach to Realizing Very Large Time Constants in Switched-Capacitor Circuits," IEEE Trans. Circuit Syst, vol.36, no. 9, pp. 1210-1216, Sep.1989.