Physical analysis of substrate noise coupling in mixed circuits in SoC technology

European Microwave Week 2010: Connecting the World, EuMIC 2010 - Conference Proceedings

Volumn , Issue , 2010, Pages 274-277

  Mohamed, Charif ^a   Barelaud, Bruno ^a   Ngoya, Edouard ^a  

^a Centre National de la Recherche Scientifique   (France)

Author keywords

[No Author keywords available]

Indexed keywords

DOPING PROFILES; FREE CARRIERS; GEOMETRIC DIMENSIONS; MIXED MODE; PHYSICAL ANALYSIS; PHYSICS-BASED; POWER LEVELS; SILICON SUBSTRATES; SILVACO; SUBSTRATE NOISE; SUBSTRATE NOISE COUPLING; SWITCHING CHARACTERISTICS; TRANSIT TIME;

SUBSTRATES;

CUTOFF FREQUENCY;

EID: 78649533616     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. J. Briaire and K.S Krish, "Principe of Substrate Crosstalk Generation in CMOS Circuit", IEEE Transaction Computer Aide Design of Integrated Circuits and System, vol. 119, n6, PP, 645-653, June, 2000.
2. H.H. Chen and D.D. Ling, "Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Design", In Proc, of IEEE DAC, PP, 738-643, Anaheim, CA, June, 1997.
3. David K. Su. Marc J. Loinaz, Shoichi Masui, and Bruce A. Wooley, "Experimental Results and modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits", IEEE Journal of Solide-State Circuits, vol. 28, No, 4, April 1993.
4. H. Veendrick, Deep-Submicron CMOS ICs, TenHagenStam editions, 2000, Chapter1, PP. 10-22.
5. C. Mhamed, B. Barelaud and E. Ngoya, "New Model of Substrate Noise Injection in Mixed-Circuits in SoC technology", Microwave Technology and Techniques Workshop European Space Agency May 2010, ESTEC The Netherland.