Improved SAT-based bounded reachability analysis

Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002

Volumn , Issue , 2002, Pages 729-734

  Ganai, M K ^a   Aziz, A ^b  

^a NEC LABORATORIES AMERICA   (United States)

^b UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; EMBEDDED SYSTEMS; MODEL CHECKING; RECONFIGURABLE HARDWARE;

GRAPH REPRESENTATION; LOGIC VERIFICATION; ON THE FLIES; REACHABILITY ANALYSIS; REDUCTION ALGORITHMS; SAT SOLVERS; SYMBOLIC SIMULATION; SYMBOLIC VALUE;

DESIGN;

EID: 78349295375     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.995020     Document Type: Conference Paper

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