A digital PLL scheme for three-phase system using modified synchronous reference frame

IEEE Transactions on Industrial Electronics

Volumn 57, Issue 11, 2010, Pages 3814-3821

  Da Silva, Carlos Henrique ^a   Pereira, Rondineli Rodrigues ^a   Da Silva, Luiz Eduardo Borges ^a   Lambert Torres, Germano ^a   Bose, Bimal K ^b   Ahn, Se Un ^c  

^a FEDERAL UNIVERSITY OF ITAJUBÁ   (Brazil)

^b University of Tennessee Knoxville   (United States)

^c Paulista Power and Light Company   (Brazil)

Author keywords

Active filter; digital signal processor (DSP); phase locked loop (PLL); synchronous reference frame (SRF)

Indexed keywords

CONTROL STRATEGIES; CONVERTING EQUIPMENT; DIGITAL PLL; DIGITAL SIGNALS; EXPERIMENTAL EVALUATION; FAST DYNAMIC RESPONSE; GRID-CONNECTED; NOISE IMMUNITY; SHUNT ACTIVE POWER FILTERS; SYNCHRONOUS REFERENCE FRAME; THREE PHASE SYSTEM; TMS320F2812; TRANSIENT RESPONSE; UNIT VECTORS; VECTOR ROTATION; VOLTAGE WAVES;

DIGITAL SIGNAL PROCESSORS; DYNAMIC RESPONSE; PHASE LOCKED LOOPS; ROTATION; SIGNAL PROCESSING; SPEED CONTROL; VECTORS;

ACTIVE FILTERS;

EID: 77957996442     PISSN: 02780046     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIE.2010.2040554     Document Type: Article

References (15)

1. B. K. Bose, Modern Power Electronics and AC Drives. Upper Saddle River, NJ: Prentice-Hall, 2001.
2. V. Kaura and V. Blasko, "Operation of a phase locked loop system under distorted utility conditions", IEEE Trans. Ind. Appl., vol. 33, no. 1, pp. 58-63, Jan./Feb. 1997.
3. L. G. B. Rolim, D. R. da Costa, and M. Aredes, "Analysis and software implementation of a robust synchronizing PLL circuit based on the pq theory", IEEE Trans. Ind. Electron., vol. 53, no. 6, pp. 1919-1926, Dec. 2006.
4. S. A. O. Silva and E. A. A. Coelho, "Analysis and design of a three-phase PLL structure for utility connected systems under distorted conditions", in Proc. 6th Int. Conf. Ind. Appl. IEEE/INDUSCON, 2004, pp. 218-223.
5. S. M. Silva, B. M. Lopes, B. J. C. Filho, R. P. Campana, and W. C. Boaventura, "Performance evaluation of PLL algorithms for singlephase grid-connected systems", in Conf. Rec. IEEE IAS Annu. Meeting, 2004, pp. 2259-2263.
6. L. N. Arruda, S. M. Silva, and B. J. C. Filho, "PLL structures for utility connected systems", in Conf. Rec. IEEE IAS Annu. Meeting, 2001, pp. 2655-2660.
7. C. H. Silva, V. F. Silva, and L. E. Borges da Silva, "Synchronous frame based controller improvement for active series filters under unbalanced conditions in three-phase four-wire systems", in Proc. 7th Int. Conf. Ind. Appl. IEEE/INDUSCON, 2006, pp. 156-160.
8. C. H. Silva, V. F. Silva, L. E. Borges da Silva, and G. Lambert-Torres, "Optimizing the series active filters under unbalanced conditions acting in the neutral current", in Proc. Int. Conf. IEEE/ISIE, 2007, pp. 943-948.
9. R. M. Santos Filho, P. F. Seixas, P. C. Cortizo, L. A. B. Torres, and A. F. Souza, "Comparison of three single-phase PLL algorithms for UPS applications", IEEE Trans. Ind. Electron., vol. 55, no. 8, pp. 2923-2932, Aug. 2008.
10. C. H. da Silva, R. R. Pereira, L. E. Borges da Silva, G. Lambert-Torres, and V. F. da Silva, "DSP implementation of three-phase PLL using modified synchronous reference frame", in Proc. 33rd IEEE/IECON, 2007, pp. 1697-1701.
11. S. Tnani, M. Mazaudier, A. Berthon, and S. Diop, "Comparison between different real-time harmonic analysis methods for control of electrical machines", in Proc. PEVD, 1994, pp. 4946-4951.
12. M. Karimi-Ghartemani and M. R. Iravani, "A method for synchronization of power electronic converters in polluted and variable-frequency environments", IEEE Trans. Power Syst., vol. 19, no. 3, pp. 1263-1270, Aug. 2004.
13. M. Karimi-Ghartemani and M. R. Iravani, "A new phase-locked loop (PLL) system", in Proc. IEEE MWSCAS, 2001, pp. 421-424.
14. Texas Instruments DSP Platforms, Nov. 2004. [Online]. Available: http://focus.ti.com/docs/prod/folders/print/tms320c2812.html
15. C. H. da Silva, R. R. Pereira, L. E. Borges da Silva, G. Lambert-Torres, and B. K. Bose, "Improving the dynamic response of shunt active power filter using modified synchronous reference frame PLL", in Proc. 34th IEEE/IECON, 2008, pp. 790-795.