Performance characteristics of strongly correlated bilayer graphene for post-CMOS logic devices

2010 Silicon Nanoelectronics Workshop, SNW 2010

Volumn , Issue , 2010, Pages

  Dellabetta, B ^a   Gilbert, M J ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

Graphene; Logic; Post CMOS; Simulation; Transport

Indexed keywords

BI-LAYER; LOGIC; LOW TEMPERATURES; NEGATIVE DIFFERENTIAL RESISTANCES; ORDERS OF MAGNITUDE; PERFORMANCE CHARACTERISTICS; POST-CMOS; QUASI PARTICLES; ROOM TEMPERATURE; SIMULATION; TRANSPORT;

LOGIC CIRCUITS; LOGIC DEVICES; NANOELECTRONICS;

GRAPHENE;

EID: 77957982428     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SNW.2010.5562544     Document Type: Conference Paper

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