High-K gate stack breakdown statistics modeled by correlated interfacial layer and high-k breakdown path

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2010, Pages 364-368

  Ribes, G ^a,b   Mora, P ^a,b   Monsieur, F ^a,b   Rafik, M ^a,b   Guarin, F ^c,d   Yang, G ^e   Roy, D ^a,b   Chang, W L ^c,d   Stathis, J ^c,d  

^a STMICROELECTRONICS   (Italy)

^b ST (ST Crolles)   (France)

^c IBM   (United States)

^d IBM T J WATSON RESEARCH CENTER   (United States)

^e GLOBALFOUNDRIES   (Singapore)

Author keywords

Breakdown; CMOS; High K metal gate dielectrics; Reliability

Indexed keywords

BREAKDOWN; CMOS; GATE STACKS; HIGH-K GATE STACKS; HIGH-K METAL GATE DIELECTRICS; INTERFACIAL LAYER;

GATES (TRANSISTOR); LOGIC GATES; RELIABILITY;

GATE DIELECTRICS;

EID: 77957909143     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2010.5488802     Document Type: Conference Paper

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