Suppression of anomalous threshold voltage increase with area scaling for Mg- or La-incorporated high-k/metal gate nMISFETs in deeply scaled region

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2010, Pages 33-34

  Morooka, T ^a   Sato, M ^a   Matsuki, T ^a   Suzuki, T ^a   Shiraishi, K ^b   Uedono, A ^b   Miyazaki, S ^c   Ohmori, K ^d   Yamada, K ^d   Nabatame, T ^e   Chikyow, T ^e   Yugami, J ^a   Ikeda, K ^a   Ohji, Y ^a  

^a SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

^b UNIVERSITY OF TSUKUBA   (Japan)

^c HIROSHIMA UNIVERSITY   (Japan)

^d WASEDA UNIVERSITY   (Japan)

^e NATIONAL INSTITUTE FOR MATERIALS SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AREA SCALING; CHANNEL WIDTHS; DEVICE STRUCTURES; HIGH-K DIELECTRIC; HIGH-K GATE DIELECTRICS; NARROW CHANNEL; OFFSET SPACERS; SCALED DEVICES;

DIELECTRIC DEVICES; ELECTRON MOBILITY; GATES (TRANSISTOR); THRESHOLD VOLTAGE;

GATE DIELECTRICS;

EID: 77957874420     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2010.5556129     Document Type: Conference Paper

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