Realistic spin-FET performance assessment for reconfigurable logic circuits

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2010, Pages 117-118

  Gao, Yunfei ^a   Augustine, Charles ^a   Nikonov, Dmitri E ^a,b   Roy, Kaushik ^a   Lundstrom, Mark S ^a  

^a Purdue University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTACT PARAMETERS; FPGA CIRCUITS; MAGNETORESISTANCE RATIO; NUMERICAL SIMULATION; PERFORMANCE ASSESSMENT; RECONFIGURABLE CIRCUITS; RECONFIGURABLE LOGIC; SLEEP TRANSISTORS; SPIN FIELD-EFFECT TRANSISTORS; SPIN RELAXATION; SPIN-FET; TUNNEL BARRIER;

DELAY CIRCUITS; ELECTRIC RESISTANCE; FIELD EFFECT TRANSISTORS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MAGNETIC FIELD EFFECTS; MAGNETORESISTANCE; RECONFIGURABLE HARDWARE; SWITCHING CIRCUITS;

VLSI CIRCUITS;

EID: 77957861436     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2010.5556193     Document Type: Conference Paper

References (8)

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