VLSI design and implementation of combined secure hash algorithm SHA-512

Communications in Computer and Information Science

Volumn 89 CCIS, Issue , 2010, Pages 105-113

  Kayalvizhi, R ^a   Harihara Subramanian, R ^a   Girish Santhosh, R ^a   Gurubaran, J ^a   Vaidehi, V ^a  

^a ANNA UNIVERSITY   (India)

Author keywords

Combined SHA 512; MAC; MD and VLSI

Indexed keywords

DIGITAL SIGNATURE; HASH ALGORITHM; HASHING ALGORITHMS; HIGH THROUGHPUT; HIGH-PERFORMANCE HARDWARE; INFORMATION SECURITY; MAC; MD AND VLSI; MESSAGE AUTHENTICATION CODES; MESSAGE DIGESTS; ON-LINE SECURITIES; SECURE HASH ALGORITHM; SHA ALGORITHM; SHA-512; SYSTEM PLATFORMS; VLSI DESIGN;

AUTHENTICATION; ELECTRONIC DOCUMENT IDENTIFICATION SYSTEMS; EMBEDDED SYSTEMS; HARDWARE; HASH FUNCTIONS;

NETWORK SECURITY;

EID: 77957556170     PISSN: 18650929     EISSN: None     Source Type: Book Series    
DOI: 10.1007/978-3-642-14478-3_11     Document Type: Conference Paper

References (5)

1. Federal Information Processing Standards Publication 180-2, August 1 (2002)
2. Aisopos, F., et al.: A Novel High-Throughput Implementation of a Partially Unrolled SHA-512. In: IEEE Melecon 2006, Benalmádena (Málaga), Spain, May 16-19 (2006)
3. Chaves, R., et al.: Cost-Efficient SHA Hardware Accelerators. IEEE Transactions on VLSI Systems 16(8) (August 2008)
4. Emam, S.A., Emami, S.S.: Design and Implementation of a Fast, Combined SHA-512 on FPGA. International Journal of Computer Science and Network Security 7(5) (May 2007)
5. Mladenov, T., Nooshabadi, S.: Implementation of Reconfigurable SHA-2 Hardware Core. In: IEEE Asia Pacific Conference on Circuits and Systems (2008)