Efficiency of dual supply voltage logic synthesis for low power in consideration of varying delay constraint strictness

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2002, Pages 701-704

  Mahnke, Torsten ^a   Panenka, Sebastian ^a   Embacher, Martin ^b   Stechele, Walter ^a   Hoeld, Wolfgang ^b  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b National Semiconductor GmbH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; COMBINATIONAL CIRCUITS; DELAY CONSTRAINTS; DUAL SUPPLY VOLTAGES; LOGIC SYNTHESIS; LOW POWER; OPTIMIZATION TECHNIQUES; POWER CONSUMPTION; POWER OPTIMIZATION; SUPPLY VOLTAGES; SUPPLY-VOLTAGE SCALING; TEST CASE; VARYING DELAY;

DELAY CIRCUITS; OPTIMIZATION;

LOGIC CIRCUITS;

EID: 77956435708     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2002.1046265     Document Type: Conference Paper

References (11)

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