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Volumn , Issue , 2010, Pages 254-257

Robust design methods for hardware accelerators for iterative algorithms in scientific computing

Author keywords

Bit width allocation; Satisfiability modulo theory

Indexed keywords

BIT-WIDTH; DATA FLOW; HARDWARE ACCELERATION; HARDWARE ACCELERATORS; ITERATIVE ALGORITHM; KEY PARTS; NUMERICAL DATA; POINT DATA; ROBUST DESIGN METHODS; SATISFIABILITY; SCIENTIFIC COMPUTING; SCIENTIFIC COMPUTING APPLICATIONS;

EID: 77956204830     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1837274.1837339     Document Type: Conference Paper
Times cited : (4)

References (12)
  • 2
    • 34247169638 scopus 로고    scopus 로고
    • HySAT: An efficient proof engine for bounded model checking of hybrid systems
    • June
    • M. Franzle and C. Herde. HySAT: An Efficient Proof Engine for Bounded Model Checking of Hybrid Systems. Formal Methods in System Design, 30(3):178-198, June 2007.
    • (2007) Formal Methods in System Design , vol.30 , Issue.3 , pp. 178-198
    • Franzle, M.1    Herde, C.2
  • 4
    • 69149088136 scopus 로고    scopus 로고
    • IEEE standard for floating-point arithmetic
    • IEEE, 29
    • IEEE. IEEE Standard for Floating-Point Arithmetic. IEEE Std 754-2008, pages 1-58, 29 2008.
    • (2008) IEEE Std 754-2008 , pp. 1-58
  • 7
    • 33847701654 scopus 로고    scopus 로고
    • Low-power optimization by smart bit-width allocation in a SystemC-based ASIC design environment
    • March
    • A. Mallik, D. Sinha, P. Banerjee, and H. Zhou. Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. IEEE Transactions on Computer-Aided Design, pages 447-455, March 2007.
    • (2007) IEEE Transactions on Computer-Aided Design , pp. 447-455
    • Mallik, A.1    Sinha, D.2    Banerjee, P.3    Zhou, H.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.