A sub-binary-weighted current calibration technique for a 2.5V 100MS/s 8bit ADC

European Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 420-423

  Mitsuishi, M ^a   Yoshida, H ^a   Sugawara, M ^a   Kunisaki, Y ^a   Nakamura, S ^a   Nakaigawa, S ^a   Suzuki, H ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

A/D CONVERSION; ANALOG TO DIGITAL CONVERTERS; CALIBRATION CIRCUITS; CALIBRATION TECHNIQUES; CURRENT CIRCUITS; LOW POWER; MEAN POWER; SMALL AREA;

ANALOG TO DIGITAL CONVERSION;

LOW POWER ELECTRONICS;

EID: 77956008466     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.1998.186298     Document Type: Conference Paper

References (6)

1. Y. Nishida et al., "An 8-bit 200Ms/s 500mW BiCMOS ADC", Proc. CICC, pp. 207-210,1995.
2. T. Miki et al., "A 10-b 50MS/s 500-mW A/D Converter using a Differential-Voltage Subconverter", IEEE J. Solid-State Circuits, Vol.29, No.4, Apr. 1994.
3. P. Vorenkamp and J. P. M. Verdaasdonk, "A 10b 50MS/s Pipelined ADC", ISSCC Dig. Tech. Papers, pp. 32-33, 1992.
4. M. Sugawara et al., "A 2.5V lOOMS/s 8bit ADC using Pre-Linearization Input Buffer and Level Up DAC/Subtractor", Symp. on VLSI Circuits Dig. Tech. Papers, 1998 (to be published).
5. Y. M. Lin et al., "A 13-b 2.5-MHz Self-Calibrated Pipelined A/D Converter in 3-um CMOS", IEEE J. Solid-State Circuits, Vol. 26, No. 4, Apr. 1991.
6. H. Ohara et al., "A CMOS Programmable Self-Calibrating 13-bit Eight-Channel Data Acquisition Peripheral", IEEE J. Solid-State Circuits, Vol. 22, No. 6, Dec. 1987.