2.5 V 100 MS/s 8 bit ADC using Pre-Linearization Input Buffer and Level Up DAC/Subtractor

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1998, Pages 170-173

  Sugawara, M ^a   Yoshida, H ^a   Mitsuishi, M ^a   Nakamura, S ^a   Nakaigawa, S ^a   Kunisaki, Y ^a   Suzuki, H ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; DIGITAL TO ANALOG CONVERSION; ELECTRIC POTENTIAL;

NOISE IMMUNITY ENCODER; PRE LINEARIZATION INPUT BUFFER;

ANALOG TO DIGITAL CONVERSION;

EID: 0031629638     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)