Low noise linear voltage regulator for use as an on-chip PLL supply in microprocessors

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 841-844

  Shor, Joseph ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT CONTROL; DIGITAL PROCESS; LEADING EDGE; LINEAR VOLTAGE REGULATORS; LOW NOISE LINEAR VOLTAGE REGULATOR; ON CHIPS; POWER SUPPLY; POWER SUPPLY REJECTION RATIO; RANDOM JITTERS;

ELECTRIC POTENTIAL; FABRICS; JITTER; POWER SUPPLY CIRCUITS; VOLTAGE REGULATORS;

VOLTAGE CONTROL;

EID: 77956005745     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537431     Document Type: Conference Paper

References (6)

1. N. Kurd, P Mosalikanti, M Neidengard, J Douglas, and R. Kumar, IEEE J. Solid State Circuits vol 44, pp. 1121, April 2009.
2. J. Shor and E. Fayneh, US Patent # 7,564,299, July 21, 2009.
3. J. S. Shor in "Voltage Regulator Circuits for Low-Jitter PLL's with High PSSR (>40dB) in a Purely Digital 65nm Process", Proceedings of IEEE COMCAS 2008, May 13-14, 2008, Tel Aviv, Israel.
4. V. Zlatkovic, US Patent 7,402,985, July 22, 2008.
5. C. Deng, N. Kurd, and G. Geannopoulos, US Patent Application 20090079406, March 26, 2009.
6. S. Ueda, US Patent 5,247,241, Sept 21, 1993.