Parallel scalable hardware architecture for hard raptor decoder

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 3741-3744

  Mladenov, T ^a   Nooshabadi, S ^a   Kim, K ^a   Dassatti, A ^b  

^a Gwangju Institute of Science and Technology (GIST)   (South Korea)

^b POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY MATRIX; DECODING ALGORITHM; EMBEDDED PROCESSORS; HARDWARE ARCHITECTURE; HARDWARE PLATFORM; HARDWARE RESOURCES; PARALLEL HARDWARE; PARAMETERIZED; PROPOSED ARCHITECTURES; SCALABLE HARDWARE ARCHITECTURE; SOFTWARE-BASED;

DATA PROCESSING; DECODING; EMBEDDED SOFTWARE; ENERGY DISSIPATION; FABRICS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

HARDWARE;

EID: 77956003452     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537741     Document Type: Conference Paper

References (9)

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4. Digital Video Broadcasting (DVB); IP Datacast over DVB-H: Content Delivery Protocols, ETSI Technical Specification, Rev. V1.2.1, 2006.
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8. T. Mladenov, S. Nooshabadi, and K. Kim, "Hardware implementation of matrix inversion for raptor decoder on embedded system," Circuits and Systems, Midwest Symposium on, vol. 0, pp. 687-690, 2009.
9. M. Luby, T. Gasiba, T. Stockhammer, and M. Watson, "Reliable multimedia download delivery in cellular broadcast networks," IEEE Trans. Broadcast., vol. 53, no. 1, pp. 235-246, March 2007.