The symmetric group in data permutation, with applications to high-bandwidth pipelined FFT architectures

IEEE Signal Processing Letters

Volumn 16, Issue 6, 2009, Pages 477-480

  Parsons, Aaron ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Discrete fourier transforms; Field programmable gate arrays; Group theory; Permutations

Indexed keywords

ABSTRACT ALGEBRA; CONFIGURABLE; DATA PERMUTATION; DATA STREAM; EFFICIENT ARCHITECTURE; GROUP THEORY; HIGH BANDWIDTH; OPEN-SOURCE LIBRARIES; PERMUTATIONS; PIPELINED FFT ARCHITECTURE; SYMMETRIC GROUPS; THEORETICAL MINIMUM; TIME SAMPLES; UTILIZATION EFFICIENCY;

ALGEBRA; ARCHITECTURE; BLOCK CODES; LOGIC GATES; SIGNAL RECEIVERS;

DISCRETE FOURIER TRANSFORMS;

EID: 77955950592     PISSN: 10709908     EISSN: None     Source Type: Journal    
DOI: 10.1109/LSP.2009.2016836     Document Type: Article

References (15)

1. W. Z. Shen, Y. H. Tai, and L. R. Dung, "On the reduction of reorder buffer size for discrete Fourier transform processor design," in Int. Symp. Circuits and Syst., London, U.K., May 1994, vol. 4, pp. 171-174.
2. A. N. Skodras and A. G. Constantinides, "Efficient input-reordering algorithms for fast DCT," Electron. Lett., vol. 27, pp. 1973-1975, Oct. 1991.
3. K. Kim, "Shuffle memory system," in Int. Symp. Parallel Proc, 1999, pp. 268-.
4. M. R. Portnoff, "An efficient parallel-processing method for transposing large matrices in place," IEEE Trans. Image Process., vol. 8, pp. 1265-1275, 1999.
5. M. Artin, Algebra. Upper Saddle River, NJ: Prentice-Hall, 1991, pp. 618-, 1991.
6. C. S. Burrus, "Unscrambling for fast dft algorithms," IEEE Trans. Acoust., Speech, Signal Process., vol. 36, no. 7, pp. 1086-1087, 1988.
7. A. Petrovsky and S. Shkredov, "Automatic generation of split-radix 2-4 parallel-pipeline fft processors: Hardware reconfiguration and core optimizations," in Int. Conf. Parallel Comp, in Elec. Eng., 2006, pp. 181-186.
8. M. Sánchez et al., "An efficient architecture for the in-place fast cosine transform," J. VLSI Signal Process., vol. 21, no. 2, pp. 91-102, 1999.
9. D. Evans, "An improved digit-reversal permutation algorithm for the fast Fourier and Hartley transforms," IEEE Trans. ASSP, vol. 35, pp. 1120-1125, 1987.
10. I. Verbauwhede et al., "In-place memory management of algebraic algorithms on application specific ics," J. VLSI Signal Process. Syst., vol. 3, no. 3, pp. 193-200, 1991.
11. A. Parsons et al., "PetaOp/second FPGA signal processing for SETI and radio astronomy," in Asilomar Conf. Sig. and Sys., Pacific Grove, CA, Nov. 2006.
12. A. Petrovsky and M. Kachinsky, "Design method of real-time parallelpipeline processors computing the vector DFT," in Int. Conf. Parallel Comp, in Elec. Eng., Sept. 1998, pp. 242-247.
13. A. Petrovsky and M. Kachinsky, "Automated parallel-pipeline structure of FFT hardware design for real-time multidimensional signal processing," in Proc. 9th Eur. Signal. Process. Conf, EUSIPCO'98, Set. 1998, vol. 2, pp. 491-494.
14. J. W. Cooley and J. W. Tukey, "An algorithm for the machine calculation of complex Fourier series," Math. Comput., vol. 19, no. 90, pp. 297-301, 1965.
15. L. R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1975, p. 777, 1975.