Automatic generation of split-radix 2-4 parallel-pipeline FFT processors: Hardware reconfiguration and core optimizations

PARELEC 2006 - Proceedings: International Symposium on Parallel Computing in Electrical Engineering

Volumn , Issue , 2006, Pages 181-186

  Petrovsky, Alexander A ^a   Shkredov, Sergei L ^b  

^a BIALYSTOK UNIVERSITY OF TECHNOLOGY   (Poland)

^b BELARUSIAN STATE UNIVERSITY OF INFORMATICS AND RADIOELECTRONICS   (Belarus)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC GENERATION; AUTOMATIC SYNTHESIS; COMPUTING ELEMENT; DESIGN RESTRICTION; FFT PROCESSORS; FIXED POINTS; FLOATING-POINT ARITHMETIC; HARDWARE OPTIMIZATION; OPERATING FREQUENCY; RE-CONFIGURABLE; REAL-TIME APPLICATION; TRANSFORM SIZE;

COMPUTER HARDWARE; DATA STRUCTURES; DESIGN; ELECTRICAL ENGINEERING; FAST FOURIER TRANSFORMS; OPTIMIZATION; PARALLEL ARCHITECTURES; PARALLEL PROCESSING SYSTEMS;

PIPELINE PROCESSING SYSTEMS;

EID: 50449099143     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PARELEC.2006.18     Document Type: Conference Paper

References (11)

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