Design of throughput-optimized arrays from recurrence abstractions

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2010, Pages 133-140

  Jacob, Arpith C ^a   Buhler, Jeremy D ^a   Chamberlain, Roger D ^a,b  

^a WASHINGTON UNIVERSITY IN ST LOUIS   (United States)

^b BECS Technology Inc   (United States)

Author keywords

Dynamic programming; FPGA; Recurrences; Systolic array; Throughput optimization

Indexed keywords

BANDWIDTH CONSTRAINT; BIOLOGICAL SEQUENCES; FPGA; FPGA DEVICES; HIGH LEVEL SYNTHESIS; MEASURE OF PERFORMANCE; MULTIPLE INPUTS; MULTIPLE ITERATIONS; NEW DESIGN; NUMBER OF ITERATIONS; OPTIMAL ARRAYS; ORDER OF MAGNITUDE; POLYHEDRAL FRAMEWORK; PROCESSING ELEMENTS; PROJECTION VECTORS; RECURRENCE EQUATION; RECURRENCES; RNA FOLDING; SMALL INPUTS; TARGET APPLICATION; THROUGHPUT OPTIMIZATION;

COMPUTER ARCHITECTURE; NANOTECHNOLOGY; OPTIMIZATION; RNA; SPACE RESEARCH; THROUGHPUT;

DYNAMIC PROGRAMMING;

EID: 77955909861     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2010.5540753     Document Type: Conference Paper

References (18)

1. Dominique Lavenier et al. Advanced Systolic Design, in Digital Signal Processing for Multimedia Systems, Parhi and Nishitani eds, March 1999.
2. S. Balev et al. Linear programming models for scheduling systems of affine recurrence equations-a comparative study. Symp. Parallel Algorithms and Architectures, 250-258, 1998.
3. Y. Wong and J.-M. Delosme. Space-optimal linear processor allocation for systolic arrays synthesis. International Parallel Proc. Symposium, 275-282, 1992.
4. A.C. Guillou et al. High level design of digital filters in mobile communications. In DATE Design Contest, March 2001.
5. Frank Hannig et al. PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. Workshop on Applied Reconfigurable Computing, March 2008.
6. K.M. Chao et al. Aligning two sequences within a specified diagonal band. Comp. Appl. Biosci., 8(5):481-487, 1992.
7. R. Nussinov et al. Algorithms for loop matchings. SIAM Journal on Appl. Math., 35(1):68-82, July, 1978.
8. P. Feautrier. Some efficient solutions to the affine scheduling problem: I. one-dimensional time. International Journal of Parallel Programming, 21(5):313-348, 1992.
9. Charles E. Leiserson, and James B.Saxe. Optimizing synchronous systems. Foundations of Comp. Sc., 23-36, 1981.
10. S Derrien et al. Combining Instruction and Loop Level Parallelism for FPGAs. Field-Programmable Custom Computing Machines, 273-282, 2001.
11. A. Jacob, J. Buhler, and R. Chamberlain. Optimal runtime reconfiguration strategies for systolic arrays. Field Programmable Logic and Application, September 2009.
12. PolyLib - A library of polyhedral functions, 2007. http://icps.u-strasbg. fr/polylib/.
13. Feautrier, P. PIP/Piplib, a parametric integer linear programming solver, 2006. http://www.piplib.org/.
14. Sven Verdoolaege et al. Counting integer points in parametric polytopes using Barvinok's rational functions. Algorithmica, 48(1):37-66, June 2007.
15. A. Jacob et al. Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs. Applicationspecific Systems, Arch. and Proc., pages 191-196, 2008.
16. A. Jacob et al. Throughput-optimal systolic arrays from recurrence equations. Washington University in St. Louis - Computer Science and Engineering Department, Tech. Rep. WUCSE-2009-39, September 2009.
17. J. Rosseel et al. An optimisation methodology for array mapping of affine recurrence equations in video and image processing. Application-specific Systems, Architectures and Processors, 415-426, August 1994.
18. Monica Lam. Software pipelining: an effective scheduling technique for VLIW machines. Conf. Prog. Lang. Design and Impl., 318-328, 1988.