The concurrent matching switch architecture

IEEE/ACM Transactions on Networking

Volumn 18, Issue 4, 2010, Pages 1330-1343

  Lin, Bill ^a   Keslassy, Isaac ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

Concurrent matching switch (CMS); high performance switches; load balanced routers; throughput guarantees

Indexed keywords

AMORTIZED TIME; CONCURRENT MATCHING SWITCH (CMS); CURRENT LOADS; DELAY ANALYSIS; HIGH CAPACITY; HIGH-PERFORMANCE SWITCHES; INTERNET ROUTERS; LINE RATE; LOAD-BALANCED ROUTERS; LOAD-BALANCED SWITCHES; NETWORK OPERATOR; PACKET REORDERING; ROUTER ARCHITECTURE; SWITCH ARCHITECTURES; SWITCH SIZE;

NETWORK ARCHITECTURE; ROUTERS; SCALABILITY; THROUGHPUT;

COMPUTER ARCHITECTURE;

EID: 77955769048     PISSN: 10636692     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNET.2010.2040289     Document Type: Article

References (25)

1. C. S. Chang, D. S. Lee, and Y. S. Jou, "Load balanced Birkhoff-von Neumann switches, Part I: One-stage buffering," Comput. Commun., vol.25, pp. 611-622, 2002.
2. C. S. Chang, D. S. Lee, and C. M. Lien, "Load balanced Birkhoff-von Neumann switches, Part II: Multi-stage buffering," Comput. Commun., vol.25, pp. 623-634, 2002.
3. I. Keslassy, S. T. Chuang, K. Yu, D. Miller, M. Horowitz, O. Solgaard, and N. McKeown, "Scaling Internet routers using optics," in Proc. ACM SIGCOMM, Karlsruhe, Germany, 2003, pp. 189-200.
4. I. Keslassy, "The load-balanced router," Ph.D. dissertation, Stanford Univ., Stanford, CA, 2004.
5. Y. Shen, S. Jiang, S.-S. Panwar, and H.-J. Panwar, "Byte-focal: A practical load-balanced switch," in Proc. IEEE HPSR, Hong Kong, May 2005, pp. 6-12.
6. C.-S. Chang, D.-S. Lee, and C.-Y. Yue, "Providing guaranteed rate services in the load balanced Birkhoff-von Neumann switches," IEEE/ACM Trans. Netw., vol.14, no.3, pp. 644-656, Jun. 2006.
7. C. S. Chang, D. S. Lee, and Y. J. Shih, "Mailbox switch: A scalable two-stage switch architecture for conflict resolution of ordered packets," IEEE Trans. Commun., vol.56, no.1, pp. 136-149, Jan. 2008.
8. C.-Y. Tu, C.-S. Chang, D.-S. Lee, and C.-T. Chiu, "Design a simple and high performance switch using a two-stage architecture," in Proc. IEEE Globecom, 2005, pp. 733-738.
9. I. Keslassy and N. McKeown, "Maintaining packet order in two-stage switches," in Proc. IEEE INFOCOM, New York, Jun. 2002, vol.2, pp. 1032-1041.
10. B. Lin and I. Keslassy, "A scalable switch for service guarantees," in Proc. 13th IEEE Symp. High-Perform. Interconnects, Aug. 17-19, 2005, pp. 93-99.
11. J. J. Jaramillo, F. Milan, and R. Srikant, "Padded frames: A novel algorithm for stable scheduling in load-balanced switches," IEEE/ACM Trans. Netw., vol.16, no.5, pp. 1212-1225, Oct. 2008.
12. J. G. Dai and B. Prabhakar, "The throughput of data switches with and without speedup," in Proc. IEEE INFOCOM, Tel-Aviv, Israel, Mar. 2000, vol.2, pp. 556-564.
13. E. Leonardi, M. Mellia, F. Neri, and M. A. Marsan, "On the stability of input-queued switches with speed-up," IEEE/ACM Trans. Netw., vol.9, no.1, pp. 104-118, Feb. 2001.
14. N. McKeown, "Scheduling algorithms for input-queued cell switches," Ph.D. dissertation, Univ. California, Berkeley, 1995.
15. Y. Li, S. Panwar, and H. J. Chao, "On the performance of a dual round-robin switch," in Proc. IEEE INFOCOM, 2001, pp. 1688-1697.
16. N. McKeown, V. Anantharan, and J. Walrand, "Achieving 100% throughput in an input-queued switch," in Proc. IEEE INFOCOM, San Francisco, CA, Mar. 1996, vol.1, pp. 296-302.
17. L. Tassiulas, "Linear complexity algorithms for maximum throughput in radio networks and input queued switches," in Proc. IEEE IN-FOCOM, New York, 1998, vol.2, pp. 533-539.
18. P. Giaccone, B. Prabhakar, and D. Shah, "Randomized scheduling algorithms for input-queued switches," IEEE J. Sel. Areas Commun., vol.21, no.4, pp. 642-655, May 2003.
19. E. Leonardi, M. Mellia, F. Neri, and M. A. Marsan, "Bounds on delays and queue lengths in input-queued cell switches," J. ACM, vol.50, no.4, pp. 520-550, Jul. 2003.
20. M. J. Neely, E. Modiano, and Y.-S. Cheng, "Logarithmic delay for N X X packet switches under the crossbar constraint," IEEE/ACM Trans. Netw., vol.15, no.3, pp. 657-668, Jun. 2007.
21. S. T. Chuang, A. Goel, N. McKeown, and B. Prabhakar, "Matching output queueing with a combined input output queued switch," IEEE J. Sel. Areas Commun., vol.17, no.6, pp. 1030-1039, Jun. 1999.
22. 2 algorithm for maximum matchings in bipartite graphs," SIAM J. Comput., pp. 225-231, Dec. 1973.
23. S. Iyer and N. McKeown, "Analysis of the parallel packet switch architecture," IEEE/ACM Trans. Netw., vol.11, no.2, pp. 314-324, Apr. 2003.
24. R. Cole, K. Ost, and S. Schirra, "Edge-coloring bipartite multigraphs in 0(Elog D) time," Combinatorica, vol.21, no.1, pp. 5-12, 2001.
25. T. Takabatake, "Another simple algorithm for edge-coloring bipartite graphs,"IEICE Trans. Fundam. Electron., Commun. Comput. Sci., vol.E88-A, no.5, pp. 1303-1304, 2005.