Built-in via module test structure for backend interconnection in-line process monitor

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2005, Pages 167-170

  Li, H Y ^a   Li, W H ^a   Wong, L Y ^a   Hwang, N ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; DEFECTS; ELECTRIC RESISTANCE; ELECTRIC RESISTANCE MEASUREMENT; FAILURE ANALYSIS; INTERCONNECTION NETWORKS; MONITORING;

BUILT-IN VIA MODULES; DEFECT IDENTIFICATION; IN-LINE PROCESS MONITORING; MODULE TEST STRUCTURE;

BUILT-IN SELF TEST;

EID: 28044441820     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. K.Honda, et al, " Integration of Interconnect Process Highly Manufacturable for 65nm CMOS Platform Technology (CMOS5)", VLSI, P62, 2004
2. Yuichi Hamamura, et al, "An Advanced Defect-Monitoring Test Structure for Electrical Measurements and Defect Localization", ICMTS, P37, 2003
3. Li Hongyu, et al, "Failure Analysis for the 0.13 μrn Cu /low K (Black Diamond ™) Interconnection by the Passive Voltage Contrast", EPTC, P342, 2003