Cost comparison for flip chip, gold wire bond, and copper wire bond packaging

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 10-13

  Palesko, Chet A ^a   Vardaman, E Jan ^b  

^a SavanSys Solutions LLC   (United States)

^b TECHSEARCH INTERNATIONAL   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVITY-BASED COST; BUILD-UP LAYERS; COPPER WIRES; COST COMPARISONS; COST EFFECTIVE; DIE BONDING; EQUIPMENT MODIFICATIONS; FLIP CHIP; FLIP-CHIP PACKAGES; GOLD WIRE; HIGH YIELD; INNER LAYER; MATERIAL COST; MOLD COMPOUNDS; PACKAGE TECHNOLOGIES; PACKAGING COSTS; POSTER PRESENTATIONS; PROCESSING COSTS; SINGULATION; SOLDER BALLS; SURFACE FINISHES; UNDERFILLS; WAFER BUMPING; WIRE BONDING;

CHIP SCALE PACKAGES; COSTS; ELECTRONIC EQUIPMENT MANUFACTURE; FLIP CHIP DEVICES; GOLD; PACKAGING; SOLDERING; SUBSTRATES; SURFACE TESTING; WAFER BONDING; WIRE;

COST BENEFIT ANALYSIS;

EID: 77955192687     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490877     Document Type: Conference Paper

References (3)

1. "Advanced Packaging Update: Market and Technology Trends," TechSearch International, Inc. Volume 2, October 2009.
2. B. Chylak, et al., "Next Generation Nickel-Based Bond Pads Enable Copper Wire Bonding," ISTC/CSTIC 2009 Packaging Technology Symposium, March 2009.
3. A. Yeoh, et al., "Copper Die Bumps (First Level Interconnect) and Low-K Dielectrics in 65nm High Volume Manufacturing," Electronic Components and Technology Conference, May 2006.