A unified method for calculating capacitive and resistive coupling exploiting geometry constraints on lightly and heavily doped CMOS processes

IEEE Transactions on Electron Devices

Volumn 57, Issue 8, 2010, Pages 1751-1760

  Bontzios, Yiorgos I ^a   Hatzopoulos, Alkis A ^a  

^a ARISTOTLE UNIVERSITY OF THESSALONIKI   (Greece)

Author keywords

CMOS integrated circuits; geometric modeling; integrated circuit noise; substrate coupling

Indexed keywords

CAPACITIVE COUPLINGS; CMOS PROCESSS; COMMERCIAL SIMULATORS; COUPLING MECHANISM; GEOMETRIC MODELING; GEOMETRY CONSTRAINTS; HEAVILY DOPED; INTEGRATED CIRCUIT NOISE; RESISTIVE COUPLINGS; SIMULATION DATA; SUBSTRATE COUPLING; SUBSTRATE COUPLINGS; TECHNOLOGY INDEPENDENT; TEST CHIPS; THEORETICAL RESULT; UNIFIED METHOD;

GEOMETRY; INTEGRATED CIRCUITS; LUMPED PARAMETER NETWORKS;

CMOS INTEGRATED CIRCUITS;

EID: 77955175629     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2050112     Document Type: Article

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